IEEE International Electron Devices Meeting 2026

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Glossary

1

IEDM

IEEE International Electron Devices Meeting, the annual IEEE Electron Devices Society conference where fabs, equipment makers and research institutes report device-level results. The 2026 edition runs 12-16 December in San Francisco.

2

Electron device

A physical structure that controls the flow of charge carriers to switch, amplify or store signals. IEDM papers span transistors, memory cells, photonic devices, sensors and quantum structures.

3

CMOS

Complementary metal-oxide-semiconductor, the paired n-type and p-type transistor logic that dominates chip manufacturing. Most IEDM logic papers are framed as CMOS scaling or CMOS-plus options.

4

FinFET

A transistor whose channel is a raised silicon fin gated on two or three sides. FinFETs remain the production baseline for many nodes discussed at the conference.

5

Gate-all-around (GAA) nanosheet

A transistor where stacked horizontal channel sheets are surrounded by the gate on all sides. GAA is the main post-FinFET production path covered in IEDM integration papers.

6

High-k metal gate (HKMG)

A gate stack combining a hafnium-based dielectric with metal electrodes to cut leakage and enable thinner equivalent oxide thickness. HKMG process details recur across IEDM device papers.

7

EUV lithography

Extreme ultraviolet patterning at roughly 13.5 nm wavelength, used for the tightest chip layers. IEDM lithography content typically covers EUV resolution, stochastics and mask effects.

8

FEOL and BEOL

Front-end-of-line covers transistor formation; back-end-of-line covers the metal interconnect stack above it. IEDM program content is usually tagged to one or both, and interconnect scaling is a standing BEOL theme.

9

TCAD

Technology computer-aided design: physics-based simulation of fabrication steps and device behavior before silicon. TCAD results are commonly paired with measured data in IEDM device papers.

10

Heterogeneous integration

Combining separately fabricated dies or materials into one package to gain function or bandwidth. It is one of the fastest-growing topic areas at recent IEDM editions.

11

Chiplet

A small die designed to be assembled with others through a die-to-die interface rather than printing one large monolithic chip. Chiplet packaging papers usually appear alongside advanced packaging sessions.

12

3D NAND

Vertical-stacked flash memory where cells are built in layers rather than shrunk laterally. IEDM papers track layer counts, string architectures and program/erase reliability.

13

DRAM

Dynamic random-access memory built from a capacitor plus access transistor per cell. Capacitor scaling, retention and row-hammer style reliability are recurring IEDM memory topics.

14

MRAM

Magnetic random-access memory storing bits in magnetic tunnel junctions. Embedded MRAM for advanced-node compatibility is a regular IEDM subject.

15

ReRAM / RRAM

Resistive RAM that switches a filament or defect path in a dielectric. It appears in IEDM work on embedded non-volatile memory and in-memory computing arrays.

16

Ferroelectric FET (FeFET)

A transistor with a ferroelectric gate dielectric that retains polarization state, giving non-volatile behavior. FeFET and ferroelectric capacitor work is presented in memory and device-physics sessions.

17

Wide-bandgap semiconductor

Materials such as SiC and GaN with a larger bandgap than silicon, enabling higher voltage and frequency operation. Power and RF device papers on these platforms are a standing IEDM track.

18

Neuromorphic computing

Hardware that mimics neural computation using analog or event-driven device arrays instead of conventional clocked logic. IEDM papers cover synaptic devices, spiking circuits and system-level benchmarks.

19

Compute-in-memory

Performing arithmetic inside memory arrays to avoid moving data across the bus. It is usually demonstrated with ReRAM, MRAM or SRAM macros reported at the conference.

20

Cryogenic CMOS

Silicon circuits characterized and modeled for operation near a few kelvin, typically to control quantum bits. It links the quantum-device and classical-circuit communities at IEDM.

21

Silicon photonics

Optical waveguides, modulators and detectors integrated on silicon for chip-to-chip or intra-datacenter links. IEDM photonics papers emphasize co-integration with CMOS.

22

Reliability (BTI, TDDB, electromigration)

Wear-out mechanisms: bias temperature instability shifts thresholds, time-dependent dielectric breakdown kills oxides, and electromigration opens metal lines. Reliability data is often the deciding evidence in IEDM integration papers.

23

Metrology

Measurement of dimensions, composition and defects during or after fabrication. New metrology approaches are frequently required before a new device can be manufactured, which is why tool vendors exhibit.

24

Plenary, oral and poster sessions

The three presentation formats used for accepted IEDM papers: invited plenary talks, timed oral slots and interactive poster sessions. Authors should check the official site for the format assigned to their paper.