Design & Verification Conference & Exhibition

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Glossary

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DVCon U.S.

The Design and Verification Conference and Exhibition, a technical event for chip design and verification professionals. The 2027 edition is scheduled for 1-4 March 2027 in Santa Clara, California.

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Design verification

The process of proving that an integrated circuit or system implementation matches its specification before manufacturing, using simulation, formal methods, emulation and prototyping.

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Functional verification

Checking that RTL or gate-level logic performs the intended function across directed and random stimulus, assertions and coverage goals.

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UVM

Universal Verification Methodology, a SystemVerilog-based framework for building reusable constrained-random testbenches with agents, sequences, scoreboards and coverage.

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SystemVerilog

A hardware description and verification language that combines RTL design constructs with assertions, coverage and object-oriented testbench features.

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Constrained random verification

A verification style that generates legal random stimulus under constraints, then measures coverage to find bugs that directed tests may miss.

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Formal verification

Mathematical proof or exhaustive exploration of design properties without simulation stimulus, often used for control logic, arbiters and protocol checks.

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Assertion-based verification

Embedding temporal properties in the design or testbench so simulators and formal tools flag illegal behavior close to the source.

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Coverage closure

The process of reaching agreed functional, code and assertion coverage goals by adding tests, constraints or justified waivers.

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Verification IP

Reusable models and testbench components that emulate standard interfaces or protocols, such as PCIe, CXL, DDR, Ethernet, USB or AMBA, so teams can verify integration faster.

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Emulation and hardware acceleration

Running design and testbench logic on specialized hardware to achieve much faster execution for large SoCs, software bring-up and long regression runs.

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FPGA prototyping

Mapping a design onto one or more FPGAs to run real workloads at near-real-time speed, often for software development and system validation.

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EDA

Electronic design automation, the software category used to design, verify, implement and sign off integrated circuits.

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CDC

Clock domain crossing analysis, which checks that signals safely cross between asynchronous clock domains and flags metastability or synchronization risks.

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Low-power verification

Checking power intent, isolation, retention and level-shifting behavior, often expressed with UPF, against simulation and formal requirements.

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Portable stimulus

A methodology for capturing verification intent once and retargeting it across simulation, emulation and prototyping platforms.

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Functional safety verification

Verification evidence and traceability used to support standards such as ISO 26262 for automotive electronics, including fault injection and safety mechanism checks.